On May 21, 2026, AMD announced that it will make more than $10 billion (about ¥1.59 trillion) in investments across Taiwan's ecosystem[1]. ※1 USD = 159 JPY The goal is to expand strategic partnerships and scale advanced packaging manufacturing for next-generation AI infrastructure[1]. As surging AI adoption drives compute demand higher, AMD is positioning itself to support rack-scale AI systems by working closely with Taiwan's manufacturing base[1][2].
More Than $10 Billion Into the Taiwan Ecosystem
According to AMD, the investment is aimed at advancing leading-edge silicon, packaging, and manufacturing technologies in collaboration with strategic partners in Taiwan[1]. The company describes the effort as building on its long-standing strengths in chiplet design, high-bandwidth memory integration, 3D hybrid bonding, and rack-scale system design[1].
Dr. Lisa Su, Chair and CEO of AMD, said that "as AI adoption accelerates, our global customers are rapidly scaling AI infrastructure to meet growing compute demand," explaining that combining AMD's high-performance computing leadership with the Taiwan ecosystem makes integrated, rack-scale AI infrastructure possible[1]. AMD frames the announcement as a move to extend, through partnerships, the silicon, packaging, and manufacturing innovations required for next-generation AI infrastructure[2].
Co-Developing EFB Packaging Technology With Taiwanese Companies
One pillar of the investment is scaling advanced packaging into volume production[1]. AMD is working with Taiwan's ASE (Advanced Semiconductor Engineering) and SPIL (Siliconware Precision Industries), along with other industry partners, to develop and qualify next-generation wafer-based 2.5D bridge interconnect technology[1]. This EFB (Elevated Fanout Bridge) architecture increases interconnect bandwidth and improves power efficiency, and is positioned as a technology that supports the 6th Gen EPYC processor codenamed "Venice"[1]. AMD says this enables greater performance-per-watt while operating within real-world power and cooling constraints[1].
There was also progress on panel-based technology. AMD announced that, together with packaging company PTI (Powertech Technology), it has qualified the industry's first 2.5D panel-based EFB interconnect[1]. The panel-based approach enables high-bandwidth interconnect at scale, leading to more efficient AI system deployment and improved overall economics[1]. On the substrate side, Taiwanese companies including Unimicron, Nan Ya PCB, and Kinsus are also collaborating on supply[1].
Building the Production Base for the Helios Platform
These technology advances will also feed into the deployment of the rack-scale platform "AMD Helios"[1]. AMD and its ecosystem partners plan to advance deployment of the Helios platform in the second half of 2026, which the company describes as a major step toward production-ready AI infrastructure[1].
ODM partners Sanmina, Wiwynn, Wistron, and Inventec are participating in building the systems[1]. These companies will help scale Helios-based systems—combining AMD Instinct MI450X GPUs, 6th Gen EPYC "Venice" CPUs, advanced networking, and the open software stack "AMD ROCm"—from design through to high-volume manufacturing[1]. Helios, powered by "Venice" and MI450X GPUs, is on track for multi-gigawatt-scale deployments beginning in the second half of 2026[1]. AIC is also contributing on the mechanical side of the rack design, with Taiwanese companies involved broadly[1].
Note that AMD's announcement contains forward-looking statements, and the features, timing, and expected benefits of the products may change[1].
Summary
Through its more than $10 billion investment in the Taiwan ecosystem, AMD is accelerating volume production of EFB packaging technology and the rollout of the Helios platform. The move deepens its ties with Taiwan's semiconductor, substrate, and assembly companies, aiming for full-scale AI infrastructure deployment heading into the second half of 2026. The actual results will need to be judged as volume production progresses.
