Chinese technology giant Alibaba Group unveiled a new self-designed AI accelerator chip called Zhenwu V900 at its annual Apsara Conference 2026 in Hangzhou on September 22, 2026. The company also outlined plans to scale its Qwen AI model family toward multi-trillion-parameter sizes, underscoring a strategy of strengthening chips, models, and cloud infrastructure together.
Claims 3x the Performance, Sharp Increase in Memory and Bandwidth
The Zhenwu V900 is the latest AI accelerator from T-Head, Alibaba's in-house chip design unit. Speaking at the keynote, Alibaba Group CEO Eddie Wu said the new chip delivers roughly three times the performance of its predecessor, the Zhenwu M890.
On the specification side, per-chip memory has grown from the M890's 144GB to 216GB, and inter-chip bandwidth has increased from 800GB/s to 1,200GB/s. More than 1,000 Zhenwu V900 chips can be linked together to operate as a single system, and a full cluster can reportedly scale up to 500,000 chips. Mass production and commercial shipping are planned for the first quarter of 2027.
Notably, Alibaba has not disclosed absolute compute figures such as FLOPS, power consumption, or the manufacturing process node. Wu's claim was limited to a relative performance multiple versus the previous generation, meaning the chip's real-world performance will likely be judged once independent benchmarks become available after mass production begins.
For comparison, rival Huawei's next-generation AI chip, the Ascend 960PR, expected in the third quarter of 2027, is said to feature 192GB of memory and 2.4TB/s of bandwidth — a sign that competition among Chinese AI chipmakers continues to intensify.
Chips, Models, and Cloud Presented as a Unified Strategy
At the Apsara Conference keynote, Alibaba framed its AI efforts around three pillars: AI models, AI chips, and AI cloud. A slide shown at the event presented five in-house chip products: the Zhenwu V900, the Yitian server CPU, the Panmai smart network interface card, the ICN Switch interconnect chip, and the Zhenyue eSSD storage controller.
On the cloud infrastructure front, Alibaba set a target of exceeding 20 gigawatts of global data center capacity by 2032. In his keynote, Wu said machine-generated "thinking" currently accounts for less than 3 percent of all thinking performed by humanity, but argued that figure could eventually exceed 1,000 times humanity's combined output — a framing that positions AI infrastructure demand as scaling with the depth of computational capability rather than population size.
Qwen Eyes Models in the 10-Trillion-Parameter Range
On the model side, Alibaba disclosed that its next-generation Qwen 4 model is currently in training, following its current flagship, Qwen 3.8-Max, which has 2.4 trillion parameters. Looking further ahead, the company said future models, Qwen 4.5 and Qwen 5, are planned to reach the 5-to-10-trillion-parameter range.
Alibaba also said it is pursuing research into "recursive self-improvement," suggesting it intends to combine ever-larger models with self-improving algorithms to push AI capability forward on two fronts simultaneously.
Set Against Intensifying US-China AI Competition
The announcement comes as US export controls on advanced chips to China remain in place, with Chinese companies racing to achieve self-sufficiency in both domestically designed semiconductors and AI models. The timing of Alibaba's announcement also coincided with scheduled high-level US-China talks, once again highlighting how central the AI technology race has become to the broader relationship between the two countries.
Alibaba has positioned the Zhenwu V900 as "the most powerful AI chip in China today," but with limited concrete performance data available, some in the industry are taking a cautious wait-and-see approach pending results from real-world deployment.
Summary
On September 22, 2026, Alibaba unveiled its new Zhenwu V900 AI chip, claiming roughly three times the performance of its predecessor along with 216GB of memory and 1,200GB/s of inter-chip bandwidth. Mass production is slated for the first quarter of 2027, with support for cluster configurations of up to 500,000 chips. The company also outlined plans to scale its Qwen model family to the 5-to-10-trillion-parameter range, reinforcing a strategy of advancing chips, models, and cloud infrastructure in tandem. Amid intensifying US-China competition in AI development, concrete verification of the chip's performance will likely hinge on future benchmark results.
