At its Advancing AI 2026 event held on July 22 and 23, 2026, AMD officially announced its 6th Gen server CPUs, the EPYC 9006 Series (codenamed Venice). Built on the new Zen 6 architecture, the flagship model reaches 256 cores and 512 threads in a single socket. It is the industry's first high-performance computing (HPC) product to enter volume production on TSMC's 2nm process.

A server CPU built for agentic AI

What AMD stressed repeatedly at the announcement was optimization for "agentic AI." Where earlier AI simply answered questions, the next wave of AI plans on its own, calls tools, writes and runs code, and reasons across enterprise data. AMD argues that this shift actually makes the CPU more important, not less. It positions the CPU as the control center that runs the agents, coordinates the work around the model, and keeps accelerators such as GPUs constantly fed with data.

Venice was designed for that control-center role. At its heart are Zen 6 generation CPU cores, offered both as standard "Zen 6" cores and as area-efficient "Zen 6c" cores. A configuration packed with Zen 6c cores reaches up to 256 cores and 512 threads, while standard Zen 6 cores top out at 96 cores and 192 threads. Manufacturing is handled by TSMC's 2nm (N2) process, starting with volume production in Taiwan and later expanding to TSMC's Arizona fab. AMD says Venice is the industry's first HPC product to enter volume production on TSMC's 2nm node.

The lineup: four purpose-built models

A defining trait of the EPYC 9006 Series is how it branches into several models by use case.

The mainstream "EPYC 9006 (Socket SP7)" is the flagship for agentic AI and cloud workloads, combining up to 256 cores and 512 threads with clock speeds of up to 5 GHz. For I/O it offers up to 128 lanes of PCIe Gen6 (64 Gbps) and a 5th-Gen Infinity Fabric that tightens CPU-to-GPU coordination. AMD says this configuration can run more AI agents per watt and per rack than the competition.

The HPC-focused "EPYC 9006X (SP7)" triples the L3 cache per core. It stacks additional 3D V-Cache to reach up to 1,152 MB in total and pushes the clock to 5.15 GHz, a setup that pays off in data-heavy scientific computing.

The efficiency-minded "EPYC 9006 (Socket SP8)" uses a flexible 8-to-128-core design suited to power-constrained racks and edge deployments. For rack-scale AI, AMD adds the "EPYC 9006 LP" (codenamed Verano), pairing up to 72 cores with LPDDR5X memory support and 112 Gbps of CPU-to-GPU bandwidth. Verano is a 2nm-generation product following Venice, positioned around performance per watt.

Performance claims and roadmap

AMD says the new generation delivers up to 1.7 times the performance of the previous platform, with memory bandwidth reaching 1.6 TB/s. AMD chair and CEO Dr. Lisa Su said that as AI and agentic workloads scale rapidly, customers need platforms that let them move from innovation to production quickly, and that AMD's close partnership with TSMC is helping make that possible. TSMC chairman and CEO Dr. C.C. Wei also commented that combining leadership process technology with advanced design innovation is what enables the next era of high-performance and AI computing.

Venice is also positioned as the CPU inside AMD's rack-scale AI system "Helios." The flagship EPYC 9006 SP7 series is slated to ship in the fourth quarter of 2026, and together with the power-efficient Verano, AMD intends to extend its 2nm-generation products across its entire data center CPU roadmap.

Summary

AMD's 6th Gen EPYC "Venice" is a server CPU that pairs the Zen 6 architecture and up to 256 cores and 512 threads with volume production on TSMC's 2nm process. It makes clear AMD's framing of the CPU as the control center for agentic AI, offering four model families tailored to different use cases. AMD claims up to 1.7 times the performance of the previous generation, with the flagship model due to ship in the fourth quarter of 2026. In an AI race where GPUs appear to be the stars, it is an announcement that underlines just how important the CPU underneath them remains.